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White Electronic Designs
WED3C755E8M-XBX
RISC MICROPROCESSOR MULTI-CHIP PACKAGE
OVERVIEW
The WEDC 755E/SSRAM multichip package is targeted for high performance, space sensitive, low power systems and supports the following power management features: doze, nap, sleep and dynamic power management. The WED3C755E8M-XBX multichip package consists of: 755 RISC processor (E die revision) Dedicated 1MB SSRAM L2 cache, configured as 128Kx72 21mmx25mm, 255 Ceramic Ball Grid Array (CBGA) Core Frequency/L2 Cache Frequency (300MHz/ 150MHz, 350MHz/175MHz) Maximum 60x Bus frequency = 66MHz
FEATURES
The WED3C755E8M-XBX is offered in Commercial (0C to +70C), industrial (-40C to +85C) and military (-55C to +125C) temperature ranges and is well suited for embedded applications such as missiles, aerospace, flight computers, fire control systems and rugged critical systems. Footprint compatible with WED3C7558M-XBX and WED3C750A8M-200BX Footprint compatible with Motorola MPC 745
This product is subject to change without notice.
FIG. 1 - MULTI-CHIP PACKAGE DIAGRAM
SSRAM P 755E SSRAM
White Electronic Designs Corp. reserves the right to change products or specifications without notice. May, 2003 Rev 2 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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FIG. 2 - BLOCK DIAGRAM
WED3C755E8M-XBX
Completion
Instruction Fetch Branch Unit
Control Unit
32K ICache
System Unit
Dispatch
BHT/BTIC
GPRs FXU1 FXU2
Rename Buffers
FPRs LSU
Rename Buffers
FPU
32K DCache
L2Tags
L2 Cache BIU
60x BIU
L2 Cache Bus
60x Bus
SSRAM
SSRAM
White Electronic Designs Corp. reserves the right to change products or specifications without notice. May, 2003 Rev 2 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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WED3C755E8M-XBX
FIG. 3 - BLOCK DIAGRAM, L2 INTERCONNECT
SSRAM 1 L2pin_DATA L2pin_DATA L2pin_DATA L2pin_DATA
L2DP0-3 L2 CLK_OUT A L2WE# L2CE# L20Vdd U1 FT# SBd# SBc# SBb# SBa# SW# ADSP# ADV# SE2
DQa DQb DQc DQd
DP0-3 K SGW# SE1#
ADSC# SE3# SA0-16 ZZ A0-16 mP 755 E SSRAM 2 U2 SA0-16 FT# SBd# SBc# SBb# SBa# SW# ADSP# ADV# SE2 L2pin_DATA L2pin_DATA L2pin_ DATA L2DP4-7 DQb ADSC# DQc DQd DP0-3 ZZ L2ZZ SE3# LBO# G# LBO# G#
L20Vdd
L2CLK_OUT B L2pin_DATA
SGW# SE1# K DQa
FIG. 4. - BLOCK DIAGRAM, L2 INTERCONNECT
TDI 755 E TDO STDI
L2 Cache SSRAM U2
L2 Cache SSRAM U1
STDO
TMS TCK TRST STMS STCK
White Electronic Designs Corp. reserves the right to change products or specifications without notice. May, 2003 Rev 2 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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FIG. 5 - PIN ASSIGNMENTS
WED3C755E8M-XBX
Ball assignments of the 255 CBGA package as viewed from the top surface.
1 A B C D E F G H J K L M N P R T
2
3 4 5 6 7 8 9 10 11 12 13 14 15 16
Side profile of the CBGA package to indicate the direction of the top surface view.
View Substrate Assembly Underfill Encapsulant Die
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PACKAGE PINOUT LISTING
Signal Name A[0-31] AACK# ABB# AP[0-3] ARTRY# AVCC BG# BR# BVSEL (4, 5, 6) CI# CKSTP_IN# CKSTP_OUT# CLK_OUT DBB# DBG# DBDIS# DBWO# DH[0-31] DL[0-31] DP[0-7] DRTRY# GBL# GND
WED3C755E8M-XBX
HRESET# INT# L1_TSTCLK (1) L2_TSTCLK (1) L2AVCC (8) L2OVCC L2VSEL (4, 5, 6, 7) LSSD_MODE# (1) MCP# NC (No-connect) OVCC (2) PLL_CFG[0-3] QACK# QREQ# RSRV# SMI# SRESET# STCK (9) STDI STDO
Pin Number C16, E4, D13, F2, D14, G1, D15, E2, D16, D4, E13, G2, E15, H1, E16, H2, F13, J1, F14, J2, F15, H3, F16, F4, G13, K1, G15, K2, H16, M1, J15, P1 L2 K4 C1, B4, B3, B2 J4 A10 L1 B6 B1 E1 D8 A6 D7 J14 N1 H15 G4 P14, T16, R15, T15, R13, R12, P11, N11, R11, T12, T11, R10, P9, N9, T10, R9, T9, P8, N8, R8, T8, N7, R7, T7, P6, N6, R6, T6, R5, N5, T5, T4 K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16, N15, N13, N14, P16, P15, R16, R14, T14, N10, P13, N12, T13, P3, N3, N4, R3, T1, T2, P4, T3, R4 M2, L3, N2, L4, R1, P2, M4, R2 G16 F1 C5, C12, E3, E6, E8, E9, E11, E14, F5, F7, F10, F12, G6, G8, G9, G11, H5, H7, H10, H12, J5, J7, J10, J12, K6, K8, K9, K11, L5, L7, L10, L12, M3, M6, M8, M9, M11, M14, P5, P12 A7 B15 D11 D12 L11 E10, E12, M12, G12, G14, K12, K14 B5 B10 C13 C3, C6, D5, D6, H4, A4, A5, A2, A3 C7, E5, G3, G5, K3, K5, P7, P10, E7, M5, M7, M10 A8, B9, A9, D9 D3 J3 D1 A16 B14 B7 C8 J16
Active High Low Low High Low -- Low Low High Low Low Low -- Low Low Low Low High High High Low Low --
I/O I/O Input I/O I/O I/O -- Input Output Input Output Input Ouput Output I/O Input Input Input I/O I/O I/O Input I/O --
I/F Voltage OVCC OVCC OVCC OVCC OVCC 2.0V OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC GND
Low Low High High -- -- High Low Low -- -- High Low Low Low Low Low -- -- --
Input Input Input Input -- -- Input Input Input -- -- Input Input Output Output Input Input Input Input Output
OVCC OVCC -- -- 2.0V L20VCC L20VCC -- OVCC -- OVCC OVCC OVCC OVCC OVCC OVCC OVCC L20VCC L20VCC L20VCC
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WED3C755E8M-XBX
PACKAGE PINOUT LISTING (continued)
Signal Name STMS (10) SYSCLK TA# TBEN TBST# TCK TDI (6) TDO TEA# TLBISYNC# TMS (6) TRST# (6) TS# TSIZ[0-2] TT[0-4] WT VCC (2) Pin Number B8 C9 H14 C2 A14 C11 A11 A12 H13 C4 B11 C10 J13 A13, D10, B12 B13, A15, B16, C14, C15 D2 F6, F8, F9, F11, G7, G10, H6, H8, H9, H11, J6, J8, J9, J11, K7, K10, L6, L8, L9 8. Active -- -- Low High Low High High High Low Low High Low Low High High Low -- I/O Input Input Input Input I/O Input Input Output Input Input Input Input I/O Output I/O Output -- I/F Voltage (7) L2OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC 2.0V
VOLDET (3) F3 NOTES: 1. These are test signals for factory use only and must be pulled up to OVCC for normal machine operation. 2. OVCC inputs supply power to the I/O drivers and VCC inputs supply power to the processor core. 3. Internally tied to GND in the BGA package to indicate to the power supply that a low-voltage processor is present. This signal is not a power supply pin. 4. To allow processor bus I/0 voltage changes, provide the option to connect BVSEL and L2VSEL independently to either OVCC or to GND . 5. Uses one of 15 existing no-connects in WEDC's WED3C750A8M-200BX. 6. Internal pull up on die. 7. OVCC supplies power to the processor bus, JTAG, and all control signals except the L2 cache controls (L2CE, L2WE, and L2ZZ); L2OVCC supplies power to the L2 cache I/O interface (L2ADDR (0-16], L2DATA (0-63), L2DP{0-7] and L2SYNC-OUT) and the L2 control signals and the SSRAM power supplies; and VCC supplies power to the processor core and the PLL and DLL (after filtering to become AVCC and L2AVCC respectively). This column serves as a reference for the nominal voltage supported on a given signal as selected by the BVSEL/ L2VSEL pin configurations and the voltage supplied. For actual recommended value of VIN or supply voltages see Recommended Operating Conditions Table.
9. 10.
-- Output -- Uses one of 20 existing VCC pins in WEDC's WED3C750A8M-200BX, no board level design changes are necessary. For new designs of WED3C755E8M-XBX refer to PLL power supply filtering. To disable SSRAM TAP controllers without interfering with the normal operation of the devices, STCK should be tied low (GND) to prevent clocking the devices. STDI and STMS are internally pulled up and may be left unconnected. Upon power-up the SSRAM devices will come up in a reset state which will not interfere with the operation of the device.
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ABSOLUTE MAXIMUM RATINGS
Characteristic Core supply voltage PLL supply voltage L2 DLL supply voltage 60x bus supply voltage L2 bus supply voltage Input supply Processor Bus L2 bus JTAG Signals Storage temperature range NOTES: 1. Functional and tested operating conditions are given in Operating Conditions table. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: VIN must not exceed OVCC by more than 0.3V at any time including during power-on reset. Symbol VCC AVCC L2AVCC OVCC L2OVCC VIN VIN VIN Tstg 3. 4. Value -0.3 to 2.5 -0.3 to 2.5 -0.3 to 2.5 -0.3 to 3.6 -0.3 to 3.6
WED3C755E8M-XBX
Unit V V V V V V V V C
Notes (4) (4) (4) (3) (3) (2) (2) (2)
-0.3 to 0VCC +0.3 -0.3 to L20VCC +0.3 -0.3 to 3.6 -55 to 150
Caution: OVCC/L2OVCC must not exceed VCC/AVCC/L2AVCC by more than 1.6 V at any time including during power-on reset. Caution: VCC/AVCC/L2AVCC must not exceed L2OVCC/OVCC by more than 0.4 V at any time including during power-on reset.
RECOMMENDED OPERATING CONDITIONS (1)
Characteristic Core supply voltage PLL supply voltage L2 DLL supply voltage Processor bus supply BVSEL = 1 voltage (2) L2 bus supply voltage (3) Input Voltage L2VSEL = 1 Processor bus JTAG Signals Symbol VCC AVCC L2AVCC OVCC L20VCC VIN VIN Recommended Value 2.0 100mV 2.0 100mV 2.0 100mV 2.5 125mV 3.3 165mV 3.3 165mV GND to OVCC GND to OVCC Unit V V V V V V V V
NOTE: 1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed 2. BVSEL = 0 is not available 3. L2VSEL = 0 is not available
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POWER CONSUMTION
WED3C755E8M-XBX
VCC=AVCC=2.00.1V, OVCC=3.3V 5% VDC, GND=0 VDC, 0Tj<105C
Processor (CPU) Frequency/L2 Frequency 300/150 MHz Full-on Mode Doze Mode Nap Mode Sleep Mode Typical Maximum Maximum Maximum Maximum 3. 4.1 6.7 2.5 1700 1200 350/175MHz 4.6 7.9 2.8 1800 1300 W W W mW mW 1, 3 1, 2 1, 2 1, 2 1, 2 Unit Notes
Sleep Mode-PLL and DLL Disabled Maximum NOTES: 1. These values apply for all valid 60x bus and L2 bus ratios. The values do not include OVCC; AVCC and L2AVCC suppling power. OVCC power is system dependent, but is typically <10% of VCC power. Worst case power consumption, for AVCC=15mW and L2AVCC=15mW. 2. Maximum power is measured at VCC=2.1V while running an entirely cacheresident, contrived sequence of instructions which keep the execution units maximally busy.
500 500 mW 1, 2 Typical power is an average value measured at VCC=AVCC=L2AVCC=2.0V, OVCC=L2OVCC=3.3V in a system, executing typical applications and benchmark sequences.
BGA THERMAL RESISTANCE
Description Junction to Ambient (No Airflow) Junction to Ball Junction to Case (Top) Symbol Theta JA Theta JB Theta JC PPC 14.2 8.6 0.1 SSRAM 11.2 5.7 0.1 Units C/W C/W C/W Notes 1 1 1
NOTE 1: Refer to PBGA Thermal Resistance Correlation at www.whiteedc.com in the application notes section for modeling conditions
L2 CACHE CONTROL REGISTER (L2CR)
The L2 cache control register, shown in Figure 5, is a supervisor-level, implementation-specific SPR used to configure and operate the L2 cache. It is cleared by hard reset or power-on reset.
FIG. 5 - L2 CACHE CONTROL REGISTER (L2CR)
L2E L2PE L2SIZ L2CLK L2RAM L2DO L2I
L2CTL L2WT L2TS
L20H
L2SL
L2DF
L2BYP
0
0
L2IO
L2CS
L2DRO
L2CTR
L2IP
0
12
34
67
8
9
10 11 12 13 14 15 16 17 18 19 20 21
22 23 24
30 31
The L2CR bits are described in Table 1.
Reserved
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TABLE 1 - L2CR BIT SETTINGS
Bit 0 Name L2E Function
WED3C755E8M-XBX
L2 enable. Enables L2 cache operation (including snooping) starting with the next transaction the L2 cache unit receives. Before enabling the L2 cache, the L2 clock must be configured through L2CR[2CLK], and the L2 DLL must stabilize. All other L2CR bits must be set appropriately. The L2 cache may need to be invalidated globally. L2 data parity checking enable. Enables parity generation and checking for the L2 data RAM interface. When disabled, generated parity is always zeros. L2 Parity is supported by WEDC's WED3C755E8M-XBX, but is dependent on application. L2 size--Should be set according to the size of the L2 data RAMs used. 11 1 Mbyte - Setting for WED3C755E8M-XBX L2 clock ratio (core-to-L2 frequency divider). Specifies the clock divider ratio based from the core clock frequency that the L2 data RAM interface is to operate at. When these bits are cleared, the L2 clock is stopped and the on-chip DLL for the L2 interface is disabled. For nonzero values, the processor generates the L2 clock and the on-chip DLL is enabled. After the L2 clock ratio is chosen, the DLL must stabilize before the L2 interface can be enabled. The resulting L2 clock frequency cannot be slower than the clock frequency of the 60x bus interface. 000 L2 clock and DLL disabled 001 / 1 010 / 1.5 011 Reserved 100 / 2 101 / 2.5 110 / 3 111 Reserved L2 RAM type--Configures the L2 RAM interface for the type of synchronous SRAMs used: * Pipelined (register-register) synchronous burst SRAMs that clock addresses in and clock data out. The 755 does not burst data into the L2 cache, it generates an address for each access. 10 Pipelined (register-register) synchronous burst SRAM - Setting for WED3C755E8M-XBX L2 data only. Setting this bit enables data-only operation in the L2 cache. For this operation, instruction transactions from the L1 Instruction cache already cached in the L2 cache can hit in the L2, but new instruction transactions from the L1 instruction cache are treated as cache-inhibited (bypass L2 cache, no L2 checking done). When both L2DO adn L2IO are set, the L2 cache is effectively locked (cache misses do not cause new entries to be allocated but write hits use the L2). L2 global invalidate. Setting L2I invalidates the L2 cache globally by clearing the L2 status bits. This bit must not be set while the L2 cache is enabled. See Motorola's User manual for L2 Invalidation procedure. L2 RAM control (ZZ enable). Setting L2CTL enables the automatic operation of the L2ZZ (low-power mode) signal for cache RAMs. Sleep mode is supported by the WED3C755E8M-XBX. While L2CTL is asserted, L2ZZ asserts automatically when the device enters nap or sleep mode and negates automatically when the device exits nap or sleep mode. This bit should not be set when the device is in nap mode and snooping is to be performed through deassertion of QACK#. L2 write-through. Setting L2WT selects write-through mode (rather than the default write-back mode) so all writes to the L2 cache also write through to the system bus. For these writes, the L2 cache entry is always marked as exclusive rather than modified. This bit must never be asserted after the L2 cache has been enabled as previously-modified lines can get remarked as exclusive during normal operation. L2 test support. Setting L2TS causes cache block pushes from the L1 data cache that result from dcbf and dcbst instructions to be written only into the L2 cache and marked valid, rather than being written only to the system bus and marked invalid in the L2 cache in case of hit. This bit allows a dcbz/dcbf instruction sequence to be used with the L1 cache enabled to easily initialize the L2 cache with any address and data information. This bit also keeps dcbz instructions from being broadcast on the system and single-beat cacheable store misses in the L2 from being written to the system bus. 0: Setting for the L2 Test support as this bit is reserved for tests. L2 output hold. These bits configure output hold time for address, data, and control signals driven to the L2 data RAMs. 00: Least Hold Time - Setting for WED3C755E8M-XBX
1 2-3 4-6
L2PE L2SIZ L2CLK
7-8
L2RAM
9
L2DO
10 11
L2I L2CTL
12
L2WT
13
L2TS
14-15
L2OH
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TABLE 1 - L2CR BIT SETTINGS
Bit 16 Name L2SL Function
WED3C755E8M-XBX
L2 DLL slow. Setting L2SL increases the delay of each tap of the DLL delay line. It is intended to increase the delay through the DLL to accommodate slower L2 RAM bus frequencies. 0: Setting for WED3C755E8M-XBX because L2 RAM interface is operated above 100 MHz. L2 differential clock. This mode supports the differential clock requirements of late-write SRAMs. 0: Setting for WED3C755E8M-XBX because late-write SRAMs are not used. L2 DLL bypass is reserved. 0: Setting for WED3C755E8M-XBX Reserved. These bits are implemented but not used; keep at 0 for future compatibility. L2 Instruction-only. Setting this bit enables instruction-only operation in the L2 cache. For this operation, data transactions from the L1 data cache already cached in the L2 cache can hit in the L2 (including writes), but new data transactions (transactions that miss in the L2) from the L1 data cashe are treated as cache-inhibited (bypass L2 cache, no L2 checking done). When both L2DO and L2IO are set, the L2 cache is effectively locked (cache misses do not cause new entries to be allocated but write hits use the L2). Note that this bit can be programmed dynamically. L2 Clock Stop. Setting this bit causes the L2 clocks to the SRAMs to automatically stop whenever the MPC755 enters nap or sleep modes, and automatically restart when exiting those modes (including for snooping during nap mode). It operates by asynchronously gating off the L2CLK_OUT [A:B] signals while in nap or sleep mode. The L2SYNC_OUT/SYNC_IN path remains in operation, keeping the DLL synchronized. This bit is provided as a power-saving alternative to the L2CTL bit and its corresponding ZZ pin, which may not be useful for dynamic stopping/restarting of the L2 interface from nap and sleep modes due to the relatively long recovery time from ZZ negation that the SRAM requires. L2 DLL rollover. Setting this bit enables a potential rollover (or actual rollover) condition of the DLL to cause a checkstop for the processor. A potential rollover condition occurs when the DLL is selecting the last tap of the delay line, and thus may risk rolling over to the first tap with one adjustment while in the process of keeping synchronized. Such a condition is improper operation for the DLL, and, while this condition is not expected, it allows detection for added security. This bit can be set when the DLL is first enabled (set with the L2CLK bits) to detect rollover during initial synchronization. It could also be set when the L2 cache is enabled (with L2E bit) after the DLL has achieved its initial lock. L2 DLL counter (read-only). These bits indicate the current value of the DLL counter (0 to 127). They are asynchronously read when the L2CR is read, and as such should be read at least twice with the same value in case the value is asynchronously caught in transition. These bits are intended to provide observability of where in the 128-bit delay chain the DLL is at any given time. Generally, the DLL operation should be considered at risk if it is found to be within a couple of taps of its beginning or end point (tap 0 or tap 128). L2 global invalidate in progress (read only)--See the Motorola user's manual for L2 Invalidation procedure.
17 18 19-20 21
L2DF L2BYP -- L2IO
22
L2CS
23
L2DRO
24-30
L2CTR
31
L2IP
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PLL POWER SUPPLY FILTERING
The AVCC and L2AVCC power signals are provided on the WED3C755E8M-XBX to provide power to the clock generation phase-locked loop and L2 cache delay-locked loop respectively. To ensure stability of the internal clock, the power supplied to the AVCC input signal should be filtered of any noise in the 500kHz to 10 MHz resonant frequency range of the PLL. A circuit similar to the one shown in Figure 6 using surface mount capacitors with minimum Effective Series Inductance (ESL) is recommended. Multiple small capacitors of equal value are recommended over a single large value capacitor. The circuit should be placed as close as possible to the AVCC pin to minimize noise coupled from nearby circuits. An identical but separate circuit should be placed as close as possible to the L2AVCC pin. It is often possible to route directly from the capacitors to the AVCC pin, which is on the periphery of the 255 BGA footprint, without the inductance of vias. The L2AVCC pin may be more difficult to route but is proportionately less critical.
WED3C755E8M-XBX
In addition, CKSTP_OUT# is an open-drain style output that requires a pull-up resistor (1 kW-5 kW) if it is used by the system. During inactive periods on the bus, the address and transfer attributes may not be driven by any master and may, therefore, float in the high-impedance state for relatively long periods of time. Since the processor must continually monitor these signals for snooping, this float condition may cause additional power draw by the input receivers on the processor or by other receivers in the system. These signals can be pulled up through weak (10 kW) pull-up resistors by the system or may be otherwise driven by the system during inactive periods of the bus to avoid this additional power draw, but address bus pull-up resistors are not neccessary for proper device operation. The snooped address and transfer attribute inputs are: A[0:31], AP[0:3], TT[0:4], TBST#, and GBL#. The data bus input receivers are normally turned off when no read operation is in progress and, therefore, do not require pull-up resistors on the bus. Other data bus receivers in the system, however, may require pull-ups, or that those signals be otherwise driven by the system during inactive periods by the system. The data bus signals are: DH[0:31], DL[0:31], and DP[0:7]. If 32-bit data bus mode is selected, the input receivers of the unused data and parity bits will be disabled, and their outputs will drive logic zeros when they would otherwise normally be driven. For this mode, these pins do not require pull-up resistors, and should be left unconnected by the system to minimize possible output switching. If address or data parity is not used by the system, and the respective parity checking is disabled through HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and should be left unconnected by the system. If all parity generation is disabled through HID0, then all parity checking should also be disabled through HID0, and all parity pins may be left unconnected by the system.
PULL-UP RESISTOR REQUIREMENTS
The WED3C755E8M-XBX requires pull-up resistors (1 kW-5 kW) on several control pins of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the processor or other bus masters. These pins are TS#, ABB#, AACK#, ARTRY#, DBB#, DBWO#, TA#, TEA#, and DBDIS#. DRTRY# should also be connected to a pull-up resistor (1 kW-5 kW) if it will be used by the system; otherwise, this signal should be connected to HRESET# to select NO-DRTRY mode. Three test pins also require pull-up resistors (100 W-1 kW). These pins are L1_TSTCLK, L2_TSTCLK, and LSSD_ MODE#. These signals are for factory use only and must be pulled up to OVCC for normal machine operation.
FIG. 6 - POWER SUPPLY FILTER CIRCUIT
10 VCC 2.2 F GND
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AVCC (or L2AVCC) 2.2 F Low ESL surface mount capacitors
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PACKAGE DESCRIPTION
Package Outline Interconnects Pitch Maximum module height Ball diameter 21x25mm
WED3C755E8M-XBX
255 (16x16 ball array less one) 1.27mm 3.90mm 0.8mm
PACKAGE DIMENSIONS 255 BALL GRID ARRAY
TOP VIEW
25.25 (0.094) MAX 0.152 (0.006) 3.14 (0.024) MAX
A1 Corner
3.04 (0.119) MAX
21.21 (0.835) MAX
BOTTOM VIEW
19.05 (0.750) BSC
T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
2.975 (0.117) REF
1.27 (0.050) BSC
19.05 (0.750) BSC
0.64 0.070 (0.025 0.003) 2.20 (0.087) MAX
0.975 (0.038) REF
0.80 (0.032) BSC
NOTES: 1. Dimensions in millimeters and paranthetically in inches. 2. A1 corner is designated with a ball missing the array.
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ORDERING INFORMATION
WED 3 C 755E 8M XBX DEVICE GRADE: M = Military Screened I = Industrial C = Commercial PACKAGE TYPE:
WED3C755E8M-XBX
-55C to +125C -40C to +85C 0C to +70C
B = 255 Ceramic Ball Grid Array CORE FREQUENCY (MHz) 350 = 350MHz/175MHz L2 cache 300 = 300MHz/150MHz L2 cache L2 CACHE DENSITY: 8Mbits = 128K x 72 SSRAM PowerPCTM: Type 755E - 'E' Die Revision (2.8) C = MULTICHIP PACKAGE 3 = PowerPCTM WHITE ELECTRONIC DESIGNS CORP.
PowerPCTM is a trademark of International Business Machine Corp.
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White Electronic Designs
WED3C755E8M-XBX
Document Title PowerPC 755 + L2 Cache Multi-Chip Package Revision History Rev # History Rev 0 Initial Release Rev 1 Changes (Pg. 1, 6, 7) 1.1 Remove 'Selects 3.3V interface' and 'Selects 2.0V interface from note 4 of package pinout listing. 1.2 Add notes 'BVSED = 0 is not available' and 'L2VSED = 0 is not available' to Recommended Operating Conditions Table Rev 2 Changes (Pg. 1, 8, 14) 1.1 Add Thermal Resistance Table on page 8 1.2 Add Revision History as page 14
Release Date September 2002 February 2003
Status Final Final
May 2003
Final
White Electronic Designs Corp. reserves the right to change products or specifications without notice. May, 2003 Rev 2 14 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

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